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KM432S2030C
CMOS SDRAM
2M x 32 SDRAM
512K x 32bit x 4 Banks Synchronous DRAM LVTTL
Revision 1.1 March 1999
Samsung Electronics reserves the right to change products or specification without notice.
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REV. 1.1 Mar. '99
KM432S2030C
Revision History
CMOS SDRAM
Revision 1.1 (March 12th, 1999)
* Corrected typo in ordering information on page 3
Revision 1.0 (March 8th, 1999) - Final Spec
* Removed KM432S2030C-Z@CL2 part (125MHz@CL2) * Changed tRDL from 1CLK to 2CLK for every clock frequency. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
Revision 0.3 (March 5th, 1999) - Preliminary Spec Revision 0.2 (February 13th, 1999)
* * * * Removed KM432S2030C-7@CL2 part (115MHz@CL2) Changed VDD condition of KM432S2030C-8@CL2 from 3.135V to 3.0V~3.6V. Changed AC Characteristic table format Add KM432S2030C-Z part.
Revision 0.1 (December 2nd, 1998)
* Delete refresh information(4K/64ms)
Revision 0.0 (November 20th, 1998)
* Define target specification.
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REV. 1.1 Mar. '99
KM432S2030C
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
* * * * 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle
CMOS SDRAM
GENERAL DESCRIPTION
The KM432S2030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
* * * * *
ORDERING INFORMATION
Part NO. KM432S2030CT-G/F6 KM432S2030CT-G/F7 KM432S2030CT-G/F8 KM432S2030CT-G/F10 Max Freq. 166MHz 143MHz 125MHz 100MHz Interface Package 86 TSOP(II)
LVTTL
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select 512K x 32 512K x 32 512K x 32 512K x 32 Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM * Samsung Electronics reserves the right to change products or specification without notice.
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KM432S2030C
PIN CONFIGURATION (Top view)
CMOS SDRAM
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C VDD DQM0 WE CAS RAS CS N.C BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD N.C DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C VSS DQM1 N.C N.C CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch)
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PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs.
CMOS SDRAM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No connection on the device.
CKE
Clock enable
A0 ~ A10 BA0,1 RAS CAS WE DQM0 ~ 3 DQ0 ~
31
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No Connection
VDD/VSS VDDQ/VSSQ NC
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE
Clock
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4 4.5 4.5 6.5 Unit pF pF pF pF
RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ31
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DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current (Inputs) Input leakage current (I/O pins) Symbol VDD, VDDQ VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -1 -1.5 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 1 1.5
CMOS SDRAM
Unit V V V V V uA uA
Note
1 2 IOH = -2mA IOL = 2mA 3 3,4
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ. 5. The VDD condition of KM432S2030C-6 is 3.135V~3.6V.
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Test Condition Burst length = 1 tRC tRC(min) IOL = 0 mA CKE VIL(max), tCC = 15ns CAS Latency 3 2 Version Unit Note -6 140 -7 130 2 mA 2 20 10 3 mA 3 30 20 3 2 3 2 200 200 180 180 2 450 150 130 160 160 130 mA 110 150 mA 150 mA uA 3 4 2 1 mA mA mA mA -8 130 130 -10 115 mA 115 1
Operating current (One bank active) Precharge standby current in power-down mode
ICC1 ICC2P
ICC2PS CKE & CLK VIL(max), tCC = ICC2N CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns
Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode Active standby current in non power-down mode (One bank active) ICC3P
ICC3PS CKE & CLK VIL(max), tCC = ICC3N ICC3NS CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0 mA Page burst 2 Banks activated tRC tRC(min)
Operating current (Burst mode)
ICC4
Refresh current
ICC5
Self refresh current
ICC6
CKE 0.2V
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. KM432S2030CT-G** 4. KM432S2030CT-F**
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AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
CMOS SDRAM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
Unit V V ns V
1200 Output 870 50pF*1 VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF*1
(Fig. 1) DC output load circuit Note : 1. The DC/AC Test Output Load of KM432S2030C-6/7 is 30pF. 2. The VDD condition of KM432S2030C-6 is 3.135V~3.6V.
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter CLK cycle time Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col.address delay Last data in to burst stop Col. address to col. address delay Mode Register Set cycle time Number of valid output data Symbol tCC(min) tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) tMRS(min) CAS Latency=3 CAS Latency=2 66 67 2 1 1 1 2 2 1 Version -6 6 12 18 18 42 -7 7 14 18 18 49 100 68 70 -8 8 16 18 18 48 -10 10 20 20 20 50 Unit ns ns ns ns ns us ns CLK CLK CLK CLK CLK ea 4 1 2,5 2 2 3 1 1 1 1 Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
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Symbol CL tCC(min) tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) 11 10 3 3 7 3 3 7 100 9 7 7 6 3 6 Version -6 3 7 -7 2 3 3 6 2 2 5 2 2 5 2 2 4 3 8 -8 2 10 3 10 -10 2 12 Unit CLK ns CLK CLK CLK CLK us CLK
CMOS SDRAM
2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS Latency=3 CAS Latency=2 CLK to valid output delay Output data CLK high pulse width CAS Latency=3 CAS Latency=2 CLK low pulse width CAS Latency=3 CAS Latency=2 Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 tSH tSLZ tSHZ tSS tCL CAS Latency=3 CAS Latency=2 tOH tCH tSAC Symbol Min CLK cycle time tCC 6 2.5 2.5
-
-6 Max 1000 5.5 Min 7 2.5 3
-7 Max 1000 5.5 Min 8 10 2.5 3
-8 Max 1000 6 7 Min 10 12 2.5 3.5
-10 Max 1000 7 8 -
Unit
Note
ns
1
ns ns ns
1, 2 2 3
2.5
-
-
3 1.75 -
-
3
-
3.5
-
ns
3
1.5
-
5.5 -
5.5 -
2 1 1 -
6 7
2.5 1 1 -
7 8
ns ns ns ns
3 3 2
1 1 -
1 1 -
Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
,
A10/AP
A9 ~ A0
Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A7) Column address (A0 ~ A7)
3 3
Bank active & row addr. Read & column address Write & column address Burst Stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes :1. OP Code : Operand code A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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KM432S2030C
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS Address BA0 ~ BA1 RFU Function A10/AP RFU A9 W.B.L A8 TM A7 A6 A5 A4 CAS Latency A3 BT
CMOS SDRAM
A2
A1 Burst Length
A0
Test Mode A8 0 0 1 1 A9 0 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved Length Burst Single Bit A6 0 0 0 0 1 1 1 1
CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved 0 1
Burst Type A3 Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8
Write Burst Length
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length : x32 (256)
POWER UP SEQUENCE
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle.
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BURST SEQUENCE (BURST LENGTH = 4)
Initial Address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 Sequential 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2
CMOS SDRAM
Interleave 2 3 0 1 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications.
CMOS SDRAM
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are thesame as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.
POWER-UP
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for both banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
BANK ADDRESSES (BA0 ~ BA1)
This SDRAM is organized as four independent banks of 524,288 words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A10)
The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0 ~ A10). The 11 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
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DEVICE OPERATIONS (Continued)
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A10 and BA0 ~ BA1 in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A3, CAS latency (read latency from column address) use A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP and BA0 ~ BA1. The write burst length is programmed using A9. A7 ~ A8, A10/AP and BA0 ~ BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
CMOS SDRAM
active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.
BANK ACTIVATE
The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be
BURST WRITE
The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. OPERATION also. See DQM
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DEVICE OPERATIONS (Continued)
DQM OPERATION
The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also.
CMOS SDRAM
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. All banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.
PRECHARGE
The precharge operation is performed on an active bank by asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1 of the bank to be precharged. The precharge command can be asserted anytime after tRAS(min) is satisfied from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state.
SELF REFRESH
The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 4096 auto refresh cycles immediately after exiting in self refresh mode.
AUTO PRECHARGE
The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write by asserting high on A10/AP, the bank is left active until a new command is asserted. Once auto precahrge command is given, no new commands are possible to that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after performing precharge to all the banks, both banks are in idle state.
- 14
REV. 1.1 Mar. '99
KM432S2030C
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1) Clock Suspended During Write (BL=4 CLK CMD CKE
Masked by CKE
CMOS SDRAM
2) Clock Suspended During Read (BL=4)
WR
RD
Masked by CKE
Internal CKE DQ(CL2) DQ(CL3) D0 D0 D1 D1 D2 D2 Not Written D3 D3 Q0 D0 Q1 Q0 Q2 Q1 Q3 Q2 Q3
Suspended Dout
2. DQM Operation
1) Write Mask (BL=4) CLK CMD DQM
Masked byDQM
2) Read Mask (BL=4)
WR
RD
DQ(CL2) DQ(CL3)
D0 D0
D1 D1
D3 D3
Q0
Masked by DQM Hi-Z
Q2 Q1
Q3 Q2
Hi-Z
Q3
DQM to Data-in Mask = 0
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) Note 2 CLK CMD CKE DQM DQ(CL2) DQ(CL3) Q0
Hi-Z Hi-Z
RD
Q2 Q1
Hi-Z Hi-Z
Q4 Q3
Hi-Z Hi-Z
Q6 Q5
Q7 Q6
Q8 Q7
*Note : 1. CKE to CLK disable/enable = 1CLK. 2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out.
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REV. 1.1 Mar. '99
KM432S2030C
3. CAS Interrupt (I)
Note 1
CMOS SDRAM
1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2) DQ(CL3)
tCCD Note 2
RD A
RD B QA0 QB0 QA0 QB1 QB0 QB2 QB1 QB3 QB2 QB3
2) Write interrupted by Write (BL=2) CLK CMD WR WR
Note 2
3) Write interrupted by Read (BL=2)
WR
tCCD
RD
Note 2
tCCD
ADD DQ
A DA0
B DB0 DB1 DQ(CL2) DQ(CL3)
A DA0 DA0
tCDL Note 3
B QB0 QB1 QB0 QB1
tCDL Note 3
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK)
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REV. 1.1 Mar. '99
KM432S2030C
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(a) CL=2, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ (b) CL=3, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ Q0
Hi-Z
Note 1
CMOS SDRAM
RD
WR
D0 RD
D1 WR
D2
D3
Hi-Z
D0
D1 WR
D2
D3
RD
Hi-Z
D0
D1 WR
D2
D3
RD
Q0
Hi-Z
Note 1
D0
D1
D2
D3
RD
WR
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
Hi-Z
D0
D1 WR
D2
D3
RD
D0
D1
D2
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
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REV. 1.1 Mar. '99
KM432S2030C
5. Write Interrupted by Precharge & DQM
CLK CMD DQM DQ D0 D1 D2 D3
Masked by DQM
CMOS SDRAM
WR
PRE
Note 2
Note 3,4
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 4. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency.
6. Precharge
1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3
tRDL Note 1,4
2) Normal Read (BL=4) CLK PRE
Note 2
CMD DQ(CL2) DQ(CL3)
RD Q0 Q1 Q0
PRE Q2 Q1 Q3 Q2
1
Q3
2
7. Auto Precharge
1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3
Note 3,4 Auto Precharge Starts
2) Normal Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD D0 D1 D0 D2 D1 D3 D2 D3
Note 3 Auto Precharge Starts
*Note : 1. tRDL : Last data in to row precharge delay 2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. 4. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency
- 18
REV. 1.1 Mar. '99
KM432S2030C
8. Burst Stop & Interrupted by Precharge
1) Normal Write (BL=4) CLK CMD DQM DQ D0 D1 D2
tRDL
CMOS SDRAM
2) Write Burst Stop (BL=8) CLK
WR
PRE
CMD DQM
WR
STOP
D3
Note 1,5
DQ
D0
D1
D2
D3
tBDL
D4
Note 2
D5
3) Read Interrupted by Precharge (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD PRE Q0 Q1 Q0
4) Read Burst Stop (BL=4) CLK CMD DQ(CL2) Q1
2
Note 3 1
RD
STOP
Q0
Q1 Q0
1
DQ(CL3)
Q1
2
9. MRS
1) Mode Register Set CLK
Note 4
CMD
PRE
tRP
MRS
2CLK
ACT
*Note : 1. tRDL : 1 CLK 2. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely. 4. PRE : All banks precharge if necessary. MRS can be issued only at all banks precharge state. 5. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency
- 19
REV. 1.1 Mar. '99
KM432S2030C
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit CLK CKE
tSS
CMOS SDRAM
2) Power Down (=Precharge Power Down) Exit CLK CKE Internal CLK RD CMD
Note 2 tSS
Internal CLK CMD
Note 1
NOP ACT
11. Auto Refresh & Self Refresh
1) Auto Refresh & Self Refresh CLK
o Note 4 Note 5 Note 3
CMD CKE
PRE
AR
o o tRP tRFC o
CMD
2) Self Refresh CLK
Note 6
o Note 4
CMD CKE
PRE
SR
CMD
o tRP o tRFC
*Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are perfomed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.
- 20
REV. 1.1 Mar. '99
KM432S2030C
12. About Burst Type Control
Sequential Counting Basic MODE Interleave Counting Random column Access tCCD = 1 CLK
CMOS SDRAM
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=1, 2, 4, 8 and full page. At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random MODE
13. About Burst Length Control
1 2 Basic MODE 4 8 Full Page At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "001". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "010". At MRS A2,1,0 = "011". At MRS A2,1,0 = "111". Wrap around mode(Infinite burst length) should be stopped by burst stop Ras interrupt or CAS interrupt At MRS A9 = "1". Read burst =1, 2, 4, 8, full page write Burst =1 At auto precharge of write, tRAS should not be violated. tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively Using burst stop command, any burst length control is possible. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued.
Special MODE Random MODE
BRSW
Burst Stop
Interrupt MODE
RAS Interrupt (Interrupted by Precharge)
CAS Interrupt
- 21
REV. 1.1 Mar. '99
KM432S2030C
FUNCTION TRUTH TABLE (TABLE 1)
Current State CS H L L IDLE L L L L L H L L Row Active L L L L L H L L Read L L L L L H L L Write L L L L L H L Read with Auto Precharge L L L L H L Write with Auto Precharge L L L L H L Precharging L L L L RAS X H H H L L L L X H H H H L L L X H H H H L L L X H H H H L L L X H H H L L X H H H L L X H H H L L CAS X H H L H H L L X H H L L H H L X H H L L H H L X H H L L H H L X H H L H L X H H L H L X H H L H H WE X H L X H L H L X H L H L H L X X H L H L H L X X H L H L H L X X H L X X X X H L X X X X H L X H L BA X X X BA BA BA X OP code X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA X X X X BA BA X X X X BA BA BA ADDR X X X CA, A10/AP RA A10/AP X OP code X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP RA, RA10 X X X X CA, A10/AP RA, RA10 X X X X CA RA A10/AP NOP NOP ILLEGAL ILLEGAL Row (& Bank) Active ; Latch RA NOP Auto Refresh or Self Refresh Mode Register Access NOP NOP ILLEGAL ACTION
CMOS SDRAM
Note
2 2 4 5 5
2
Begin Read ; latch CA ; determine AP Begin Write ; latch CA ; determine AP ILLEGAL Precharge ILLEGAL NOP (Continue Burst to End --> Row Active) NOP (Continue Burst to End --> Row Active) Term burst --> Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Reads ILLEGAL NOP (Continue Burst to End --> Row Active) NOP (Continue Burst to End --> Row Active) Term burst --> Row active Term burst, New read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, precharge timing for Writes ILLEGAL NOP (Continue Burst to End --> Precharge) NOP (Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End --> Precharge) NOP (Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after tRPL 2 2 2 4 2 2 3 3 2 3 3 2 2
- 22
REV. 1.1 Mar. '99
KM432S2030C
FUNCTION TRUTH TABLE (TABLE 1)
Current State CS L H L Row Activating L L L L L H L Refreshing L L L H Mode Register Accessing L L L L RAS L X H H H L L L X H H L L X H H H L CAS L X H H L H H L X H L H L X H H L X WE X X H L X H L X X X X X X X H L X X BA X X X X BA BA BA X X X X X X X X X X X ADDR X X X X CA RA A10/AP X X X X X X X X X X X ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after tRFC NOP --> Idle after tRFC ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after 2 clocks NOP --> Idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL ACTION
CMOS SDRAM
Note
2 2 2 2
Abbreviations : RA = Row Address NOP = No Operation Command
BA = Bank Address CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clcok and the current clock cycle. 2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle.
- 23
REV. 1.1 Mar. '99
KM432S2030C
FUNCTION TRUTH TABLE (TABLE 2)
Current State CKE (n-1) H L Self Refresh L L L L L H All Banks Precharge Power Down L L L L L L H H H H All Banks Idle H H H H L Any State other than Listed above H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L H L H L CS X H L L L L X X H L L L L X X H L L L L L L X X X X X RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X WE X X H L X X X X X H L X X X X X H L X H H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X RA X OP Code X X X X X INVALID
CMOS SDRAM
ACTION
Note
Exit Self Refresh --> Idle after tRFC (ABI) Exit Self Refresh --> Idle after tRFC (ABI) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL Row (& Bank) Active Enter Self Refresh Mode Register Access NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clcok Suspend
6 6
7 7
8 8
8
9 9
Abbreviations : ABI = All Banks Idle, RA = Row Address *Note : 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restarts internal clock. A minimum setup time 1CLK + tSS must be satisfied before any command other than exit. 8. Power down and self refresh can be entered only from the both banks idle state. 9. Must be a legal command.
- 24
REV. 1.1 Mar. '99
KM432S2030C
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
CMOS SDRAM
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCL tCC HIGH
*Note 1
CKE CS
tRCD tSH
tRAS tRC
tSH
tSS
tRP
RAS
tSS tCCD tSH
CAS
tSH tSS Ca Cb Cc Rb
ADDR
Ra tSS
*Note 2
*Note 2,3
*Note 2,3
*Note 2,3 *Note 4
*Note 2
BA0 ~ BA1
BS
BS
BS
BS
BS
BS
A10/AP
Ra
*Note 3
*Note 3
*Note 3 *Note 4
Rb
tRAC tSAC
tSH Qa Db tSS tOH tSH Qc
DQ
tSLZ
WE
tSS tSS tSH
DQM
Row Active
Read
Write
Read Precharge
Row Active
: Don't care
REV. 1.1 Mar. '99
KM432S2030C
CMOS SDRAM
0
1
*Note : 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
BA0 0 0 1 1
BA1 0 1 0 1
Active & Read/Write Bank A Bank B Bank C Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command A10/AP BA0 BA1 0 0 0 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 Operation Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Disable auto precharge, leave bank C active at end of burst. Disable auto precharge, leave bank D active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Enable auto precharge, precharge bank C at end of burst. Enable auto precharge, precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted. A10/AP BA0 BA1 0 0 0 0 1 0 0 1 1 x 0 0 1 1 x Precharge Bank A Bank B Bank C Bank D All Banks
REV. 1.1 Mar. '99
KM432S2030C
Power Up Sequence
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CKE CS
High level is necessary o tRP tRC o o tRC o o
RAS
o
o
o o
CAS
o
ADDR
o o
o o
Key
RAa
BA0
o o
o o
BA1
o o
o o
A10/AP
o o High-Z
o o
RAa
DQ
WE
o o
o o
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (A-Bank)
: Don't care
REV. 1.1 Mar. '99
KM432S2030C
Read & Write Cycle at Same Bank @Burst Length=4
0 CLOCK CKE
tRC
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
*Note 1
CS
tRCD
RAS
*Note 2
CAS ADDR BA0 BA1 A10/AP
Ra Rb Ra Ca Rb Cb
tOH
CL=2
tRAC
*Note 3
Qa0 tSAC
Qa1
Qa2
Qa3 tSHZ
*Note 4
Db0
Db1
Db2
Db3 tRDL
*Note 5
DQ
tOH
CL=3
tRAC
*Note 3
Qa0 tSAC
Qa1
Qa2
Qa3 tSHZ
*Note 4
Db0
Db1
Db2
Db3 tRDL
*Note 5
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) 5. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency
REV. 1.1 Mar. '99
KM432S2030C
Page Read & Write Cycle at Same Bank @Burst Length=4
0 CLOCK CKE CS
tRCD
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAS
*Note 2
CAS
ADDR
Ra
Ca
Cb
Cc
Cd
BA0
BA1
A10/AP
Ra tRDL
*Note 4
CL=2 DQ CL=3
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
tCDL
WE
*Note 1 *Note 3
DQM
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank) : Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency
REV. 1.1 Mar. '99
KM432S2030C
Page Read Cycle at Different Bank @Burst Length=4
0 CLOCK CKE
*Note 1
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
CS RAS
*Note 2
CAS ADDR BA0
RAa RBb CAa RCc CBb RDd CCc CDd
BA1
A10/AP
RAa
RBb
RCc
RDd
CL=2 DQ CL=3
QAa0 QAa1 QAa2 QBb0
QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0
QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE DQM
Row Active (A-Bank)
Read (A-Bank) Row Active (B-Bank)
Read (B-Bank) Row Acive (C-Bank)
Read (C-Bank) Row Active (D-Bank)
Read (D-Bank) Precharge (C-Bank)
Precharge (D-Bank)
Precharge (A-Bank)
Precharge (B-Bank) : Don't care
*Note :
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
REV. 1.1 Mar. '99
KM432S2030C
Page Write Cycle at Different Bank @Burst Length=4
0 CLOCK CKE CS HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
RAS
*Note 2
CAS
ADDR
RAa
RBb
CAa
CBb
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
RAa
RBb
RCc
RDd
DQ
DAa0 DAa1 DAa2
DAa3
DBb0 DBb1
DBb2 DBb3
DCc0 DCc1 DDd0 DDd1 DDd2
tCDL
tRDL
*Note 3
WE
*Note 1
DQM
Row Active (A-Bank)
Write (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (C-Bank)
Row Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
: Don't care
*Note :
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. 3.For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency
REV. 1.1 Mar. '99
KM432S2030C
Read & Write Cycle at Different Bank @Burst Length=4
0 CLOCK CKE CS RAS HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CAS
ADDR
RAa
CAa
RDb
CDb
RBc
CBc
BA0
BA1
A10/AP
RAa
RBb
RAc tCDL
*Note 1
CL=2 DQ CL=3
QAa0 QAa1
QAa2 QAa3
DDb0
DDb1 DDb2 DDb3
QBc0
QBc1 QBc2
QAa0 QAa1 QAa2 QAa3
DDb0
DDb1 DDb2 DDb3
QBc0
QBc1
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (D-Bank)
Write (D-Bank) Precharge (B-Bank)
Read (B-Bank)
: Don't care
*Note :
1. tCDL should be met to complete write.
REV. 1.1 Mar. '99
KM432S2030C
Read & Write Cycle with Auto Precharge I @Burst Length=4
0 CLOCK CKE CS RAS CAS ADDR BA0 BA1 A10/AP DQ (CL=2)
RAa RAa RBb CAa CBb
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RBb
DBb0 DBb1 DBb2 DBb3
QAa0 QAa1 QAa2 QAa3
DQ (CL=3)
QAa0 QAa1 QAa2 QAa3
DBb0
DBb1 DBb2 DBb3
WE
DQM
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
: Dont care
*Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2, BRSW mode and Block write)
REV. 1.1 Mar. '99
KM432S2030C
Read & Write Cycle with Auto Precharge II @Burst Length=4
0 CLOCK CKE CS HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
Ra
Ca
BA0
BA1
A10/AP
Ra
Rb
Ra
DQ
CL=2
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Da0
Da1
CL=3
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Da0
Da1
WE
DQM
Row Active (A-Bank)
Read with Auto Pre charge (A-Bank) Row Active (B-Bank)
Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank)*
Precharge (B-Bank)
Row Active (A-Bank)
Write with Auto Precharge (A-Bank)
: Don't care *Note: * When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at B Bank read command input point . - any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
REV. 1.1 Mar. '99
KM432S2030C
Read & Write Cycle with Auto Precharge III @Burst Length=4
0 CLOCK CKE CS HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
DQ
CL=2
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
CL=3
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
WE
DQM
* Row Active (A-Bank) Read with Auto Precharge (A-Bank) Auto Precharge Start Point (A-Bank) Row Active (B-Bank) Read with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank)
: Don't care *Note : * Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point
REV. 1.1 Mar. '99
KM432S2030C
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA0
BA1
A10/AP
Ra
DQ
Qa0
Qa1
Qa2
Qa3 tSHZ
Qb0
Qb1 tSHZ
Dc0
Dc2
WE
*Note 1
DQM
Row Active
Read
Clock Suspension
Read
Read DQM Write
Write DQM Clock Suspension
Write DQM
: Don't care *Note : 1. DQM is needed to prevent bus contention.
REV. 1.1 Mar. '99
KM432S2030C
CMOS SDRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page
0 CLOCK CKE CS HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
1
1 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=2 DQ
QAa0 QAa1 QAa2 QAa3 QAa4
2
2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=3
QAa0 QAa1 QAa2 QAa3 QAa4
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
: Don't care
*Note :
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length.
REV. 1.1 Mar. '99
KM432S2030C
CMOS SDRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa tBDL
*Note 2,4
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DQ
DAa0 DAa1 DAa2 DAa3 DAa4
WE
DQM
Row Active (A-Bank) *Note :
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
: Don't care 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. 4. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency.
REV. 1.1 Mar. '99
KM432S2030C
Burst Read Single bit Write Cycle @Burst Length=2
0 CLOCK
*Note 1
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE CS
HIGH
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RCc
CBc
CCd
BA0
BA1
A10/AP
RAa
RBb
RAc
CL=2 DQ CL=3
DAa0
QAb0
QAb1
DBc0
QCd0 QCd1
DAa0
QAb0
QAb1
DBc0
QCd0 QCd1
WE
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank)
Row Active (C-Bank) Write with Auto Precharge (B-Bank)
Read (C-Bank)
Precharge (C-Bank)
Read with Auto Precharge (A-Bank)
: Don't care
*Note :
1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
REV. 1.1 Mar. '99
KM432S2030C
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0 CLOCK
tSS
CMOS SDRAM
1
2
3
o o
4
5
6
7
8
9
o
10
11
12
13
14
15
16
17
18
19
tSS
*Note 2
CKE
*Note 1
tSS o
*Note 2
*Note 3
CS
o o
o
RAS
o o
o o
CAS
o o
o o
ADDR
o o
Ra
o o
Ca
BA
o o
o o
A10/AP
o o
Ra
o o tSHZ
DQ
o
o
Qa0
Qa1
Qa2
WE
o o
o o
DQM
o o
o o
Precharge Power-down Entry
Row Active
Read
Precharge
Precharge Power-down Exit
Active Power-down Entry
Active Power-down Exit
: Don C t Care
*Note :
1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. 3. Can not violate minimum refresh specification. (64ms)
REV. 1.1 Mar. '99
KM432S2030C
Self Refresh Entry & Exit Cycle
0 CLOCK
*Note 2 *Note 1
CMOS SDRAM
1
2
3
4
5
6
o o
7
8
9
10
11
*Note 4
12
13
14
15
16
17
18
19
o tRCmin
*Note 6
CKE
o tSS
*Note 3
o
CS
o o
*Note 5
o
RAS
o o
o o
*Note 7
CAS
o o
o o
ADDR
o o
o o
BA0~BA1
o o
o o
A10/AP
o o
o o
DQ
Hi-Z
o
Hi-Z
o
WE
o o
o o
DQM
o o
o o
Self Refresh Entry
Self Refresh Exit
Auto Refresh : Don't care
*Note :
TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System colck restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
REV. 1.1 Mar. '99
KM432S2030C
Mode Register Set Cycle
0 CLOCK CKE CS
*Note 2
CMOS SDRAM
Auto Refresh Cycle
6 7 8 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16
o
1
2
3
4
5
8 17
9 18
10 19
HIGH
HIGH
o
o
tRC
RAS
*Note 1
o o o
CAS
o o
*Note 3
ADDR
Key
Ra
o o
DQ
Hi-Z
Hi-Z
o
WE
o o
DQM
o o
MRS
New Command
Auto Refresh
New Command
: Don't care
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table.
REV. 1.1 Mar. '99
KM432S2030C
PACKAGE DIMENSIONS
CMOS SDRAM
86-TSOP2-400F
Unit : Millimeters
0~8C 0.25 TYP 0.010 #86 #44 0.45~0.75 0.018~0.030
11.760.20 0.4630.008
0.125+0.075 -0.035 0.005+0.003 -0.001
22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.61 ) 0.024 0.20
+0.10 -0.03 0.10 0.004
0.21 0.008
0.05 0.002
1.00 0.039
0.10 0.004
1.20 MAX 0.047
0.50 0.0197
0.05 MIN 0.010
- 43
REV. 1.1 Mar. '99
( 0.50 ) 0.020
#1
#43
10.16 0.400

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